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asix electronics corporation 2f, no.13, industry east rd. ii, science-based industrial park, hsin-chu city, taiwan, r.o.c. tel: 886-3-579-9500 fax: 886-3-579-9558 ax8886 0 100base-tx/fx repeater controlle r a s i x asix AX88860 10/100base-tx/fx repeater controller data sheet(11/03/?97) document no. : ax860d2.doc this data sheets contain new products information. asix electronics reserves the rights to modify the products specification without notice. no liability is assumed as a result of the use of this product. no rights under any patent accompany the sale of the product.
AX88860 preliminary asix electronics corporation 2 contents 1.0 AX88860 overview ................................................................................................................................ .............. 4 1.1 g eneral d escription ................................................................................................................................ ............ 4 1.2 f eatures ................................................................................................................................................................ . 5 1.3 b lock d iagram ................................................................................................................................ ...................... 6 1.4 p in c onnection d iagram ( mode 0) ................................................................................................ ...................... 7 1.5 p in c onnection d iagram ( mode 1) ................................................................................................ ...................... 8 2.0 pin description ................................................................................................................................ .................. 9 2.1 s hared mii interface ................................................................................................................................ ........... 9 2.2 d edicated mii interface ................................................................................................................................ ... 10 2.3 e xpansion b us i nterface ................................................................................................................................ ... 11 2.4 led d isplay ................................................................................................................................ ......................... 12 2.5 m iscellaneous ................................................................................................................................ ..................... 13 3.0 functional description ................................................................................................ ........................... 14 3.1 r epeater s tate m achine ................................................................................................................................ .... 15 3.2 rxe /txe control ................................................................................................................................ ......... 15 3.3 j abber s tate m achine ................................................................................................................................ ........ 16 3.4 p artition s tate m achine ................................................................................................................................ ... 16 3.5 e xpansion l ogic (c ascade i nterface ) ................................................................................................ .............. 16 3.6 d ata f low control ................................................................................................................................ ............ 17 3.7 rid r eceive -t ransmit i nterface (d aisy c hain l ogic ) ................................................................ .................. 17 3.8 led d isplay i nterface ................................................................................................................................ ...... 17 4.0 internal registers ................................................................................................................................ ....... 19 4.1 c onfiguration r egister (config) ................................................................................................ .................. 19 4.2 r epeater id r egister (rptr_id) ................................................................................................ ....................... 19 5.0 electrical specification and timing ................................................................ ............................... 20 5.1 a bsolute m aximum r atings ................................................................................................ .............................. 20 5.2 g eneral o peration c onditions ................................................................................................ ........................ 20 5.3 dc c haracteristics ................................................................................................................................ ............ 20 5.4 ac specifications ................................................................................................................................ ................ 21 5.4.1 mii interface timing tx & rx ................................................................................................ ........................ 21 5.4.2 expansion bus ................................................................................................................................ ................. 22 5.4.3 led display ................................................................................................................................ ................. 23 5.4.4 led display after reset ................................................................................................................................ 23 5.4.5 repeater id daisy chain ................................................................................................................................ 24 6.0 package information ................................................................................................................................ . 25
AX88860 preliminary asix electronics corporation 3 figures f ig - 1 c hip b lock d iagram ................................................................................................................................ ........... 6 f ig - 2 p in c onnection d iagram for mode 0 ................................................................................................ ............... 7 f ig - 3 p in c onnection d iagram for mode 1 ................................................................................................ ................ 8 f ig - 4 f unctional b lock d iagram ................................................................................................ ............................ 14 f ig - 5 a pplication for led display ................................................................................................ .......................... 18
AX88860 preliminary asix electronics corporation 4 1.0 AX88860 overview the AX88860 10/100mbps repeater controller is design for low cost dumb hub application. the AX88860 directly supports up-to night 10/100mbps links with its shared 8 ports mii interfaces and 1 dedicated mii interface. maximum up-to 72 ports can be constructed when using expansion bus cascades 8 AX88860s. the AX88860 is designed base on ieee 802.3u clause 27 ? repeater for 100mb/s base-band networks? . it is fully compatible with ieee 802.3u standard = . 1.1 general description the AX88860 repeater controller is a subset of a repeater set containing all the repeater-specific components and functions, exclusive of phy components and functions. the AX88860 has only media independent interface (mii) to connect to phy devices. other then ax88850 serial chips that has 2 kinds of interfaces. there are physical coding sub-layer (pcs) interface and media independent interface (mii). the AX88860 supports one shared bus (8 ports) mii interfaces, 1 dedicated mii ports interface, a port expansion interface and led display interface. the AX88860 dedicated mii ports can connect to phy or optional directly connect to 2 ports bridge, switch or mac that has standard mii interface. the AX88860 has two application modes. mode 0 single chip repeater application. mode 1 multiple chips cascaded repeater application. = note : to simplify the design of 10base ethernet repeater. the portion of 10mb/p repeater will follow the specification as below : (1) the phy interface defines as standard mii interface with 2.5mhz transmit and receive clock and 4 bits data format. (2) the repeater core state machine follow ieee 802.3u clause 27 ? repeater for 100 mb/s baseband networks ? with ten times of time scale. it is important that it is no longer follows the legacy 10base repeater state machine.
AX88860 preliminary asix electronics corporation 5 1.2 features ieee 802.3u repeater compatible supports 10/100 mbps alternative supports 8+1 network connections 8 ports share mii interfaces direct interface to phy chip with mii interface 1 dedicated mii interfaces can also support 100base-t4/fx phy interfaces the 1 dedicated mii interfaces can also easily connect to bridging device with mii interface up-to 8 repeater chips can be cascaded for large hub application low latency design supports class ii repeater implementation with large port number all ports can be separately isolated or partitioned in response to fault condition separate jabber and partition state machines for each port encoded or direct led drivers per-port led display for jabber, partition, activity. global collision, utilization and collision (%) presentation power on led diagnosis. all the led display will follow the ?on-off-on-off- normal? operation procedure during/after power on reset ( mode 1 only ). 100-pin pqfp
AX88860 preliminary asix electronics corporation 6 1.3 block diagram q- ph y phy mii i/f mii inte rf ace reconcil ia - t io n la yer po rt 0 - po rt 7 mii po rt 8 elastici ty buffer mux r ep eate r state machine collis io n h andling l ogic per port jabber c tl, auto-part it io n s m & per port collis io n , pa rt it io n c ounte rs . setup r eg ist e rs cas ca de a rb i tr a tio n logic ... ..... q- ph y mii i/f led display fig - 1 chip block diagram
AX88860 preliminary asix electronics corporation 7 1.4 pin connection diagram (mode 0) 1 5 6 4 7 2 3 8 9 10 11 12 13 14 15 16 17 18 19 23 24 22 20 21 48 49 50 51 52 asix AX88860 ( mode 0) 25 29 30 28 31 26 27 32 33 34 35 36 37 38 39 40 41 42 43 47 46 44 45 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 100 99 97 98 96 95 94 93 92 91 90 86 85 84 83 82 81 53 vdd nc dcrs vss drxd2 drxd1 drx_clk vss vdd drx_er drxd0 dtx_en drx_dv vdd drxd3 /lact<0> /luti<3> test /luti<4> /lcol /rst vss lclk /luti<5> vdd vss nc col vss vss vss vdd vss rxd0 rxd1 rxd2 rxd3 rxer rx_clk rx_dv txd0 txd1 txd2 txd3 txer crs0 crs1 crs2 crs3 txen0 txen1 txen2 txen3 rxen0 crs4 crs5 crs6 crs7 rxen1 rxen2 rxen3 txen4 txen5 txen6 txen7 rxen4 rxen5 rxen6 rxen7 vss nc vdd 88 89 87 vss vss vss vss mode vdd /bridge b100 /luti<0> /luti<1> /luti<2> /lpart<0> /lpart<1> /lpart<2> /lpart /lpart<3> /lpart<4> /lpart<5> /lpart<6> /lpart<7> /lact<1> /lact<2> /lact<3> /lact<4> /lact<5> /lact<6> /lact<7> /lact fig - 2 pin connection diagram for mode 0
AX88860 preliminary asix electronics corporation 8 1.5 pin connection diagram (mode 1) 1 5 6 4 7 2 3 8 9 10 11 12 13 14 15 16 17 18 19 23 24 22 20 21 48 49 50 51 52 asix AX88860 ( mode 1) 25 29 30 28 31 26 27 32 33 34 35 36 37 38 39 40 41 42 43 47 46 44 45 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 100 99 97 98 96 95 94 93 92 91 90 86 85 84 83 82 81 53 vdd col dcrs vss drxd2 drxd1 drx_clk vss vdd drx_er drxd0 dtx_en drx_dv vdd drxd3 ird_odir ird<2> ird<0> /ir_acti<4> ird<1> led_ck test rid<0> /ird_v rid<2> /rst vss lclk ird<3> rid<1> vdd vss /ir_acto<7> rst_dly daisy_out daisy_in nc vss vss vss vdd vss rxd0 rxd1 rxd2 rxd3 rxer rx_clk rx_dv txd0 txd1 txd2 txd3 txer crs0 crs1 crs2 crs3 txen0 txen1 txen2 txen3 rxen0 crs4 crs5 crs6 crs7 rxen1 rxen2 rxen3 txen4 txen5 txen6 txen7 rxen4 rxen5 rxen6 rxen7 /ir_acti<3> /ir_acti<2> /ir_acti<1> /ir_acti<0> /ir_acti<5> /ir_acti<6> /ir_acti<7> /ir_acto<6> /ir_acto<5> /ir_acto<4> /ir_acto<3> /ir_acto<2> /ir_acto<1> /ir_acto<0> vss /dis_daisy /dis_dmii vdd 88 89 87 /ird_er ird_ck vss vss vss vss mode vdd /bridge b100 led<0> led<2> led<1> fig - 3 pin connection diagram for mode 1
AX88860 preliminary asix electronics corporation 9 2.0 pin description 2.1 shared mii interface signal name type pin no. description tx_er o/mh 66 transmit error : tx_er is transition synchronously with respect to the rising edge of tx_clk . asserted high when a code violation is request to be send txd[3:0] o/mh 63-60 transmit data : txd[3:0] is transition synchronously with respect to the rising edge of tx_clk. for each tx_clk period in which tx_en is asserted, txd[3:0] are accepted for transmission by the phy. tx_en[7:0] o/l 80-79 77-76 45-42 transmit enable : tx_en is transition synchronously with respect to the rising edge of tx_clk. tx_en indicates that the port is presenting nibbles on txd [3:0] for transmission. rxd[3:0] i/pu 55-54 52-51 receive data : rxd [3:0] is driven by the phy synchronously with respect to rx_clk. rx_er i/pd 56 receive error : rx_er ,is driven by phy and synchronous to rx_clk, is asserted for one or more rx_clk periods to indicate to the port that an error has detected. rx_clk i 57 receive clock : rx_clk is a continuous clock that provides the timing reference for the transfer of the rx_dv,rxd [3:0] and rx_er signals from the phy to the mii port of the repeater. rx_dv i/pd 58 receive data valid : rx_dv is driven by the phy synchronously with respect to rx_clk. asserted high when valid data is present on rxd [3:0]. crs[7:0] i/pd 70-67, 37-34 carrier sense : asynchronous signal crs is asserted by the phy when either the transmit or receive medium is non-idle. rx_en[7:0] o/l 75-74 72-71, 50-47 receive enable : assert high to the respective phy chip to enable its receive data. note : ?type? has the following attributes i : input o : output i/o : bi-direction pu : pull up pd : pull down h : driving high current 16ma mh : driving middle high current 12ma ml : driving middle low current 8ma l : driving low current 4ma
AX88860 preliminary asix electronics corporation 10 2.2 dedicated mii interface signal name type pin no. description drxd[3:0] or /ir_acti[3:0] i/pu 85-82 receive data : drxd [3:0] is driven by the phy synchronously with respect to drx_clk. inter repeater activity in: these pins perform the same function as /ir_acto[3:0] when they serve as input function. then the /ir_acto[7:0] insert external buffers the input function must be replaced with /ir_acti [3:0]. dcrs or /ir_acti[4] i/pd 87 carrier sense : asynchronous signal dcrs is asserted by the phy when either the transmit or receive medium is non-idle. /ir_acti[4] : see above /ir_acti[3:0] descriptions. drx_dv or /ir_acti[5] i/pd 88 receive data valid : drx_dv is driven by the phy synchronously with respect to drx_clk. asserted high when valid data is present on drxd [3:0]. /ir_acti[5] : see above /ir_acti[3:0] descriptions. drx_er or /ir_acti[6] i/pd 89 receive error : drx_er ,is driven by phy and synchronous to drx_clk, is asserted for one or more rx_clk periods to indicate to the port that an error has detected. /ir_acti[6] : see above /ir_acti[3:0] descriptions. drx_clk or /ir_acti[7] i 90 receive clock : drx_clk is a continuous clock that provides the timing reference for the transfer of the drx_dv,drxd [3:0] and drx_er signals from the phy to the mii port of the repeater. /ir_acti[7] : see above /ir_acti[3:0] descriptions. dtx_en /dis_daisy i/o /pu/l 81 transmit enable : dtx_en is transition synchronously with respect to the rising edge of tx_clk(lclk). dtx_en indicates that the port is presenting nibbles on txd [3:0] for transmission. /dis_daisy : default pull-up to enable daisy chain function. to disable daisy chain function pull the pin down external. /dis_dmii or nc i/pu 4 disable dedicated mii port: when mode= ? 1 ? , the dedicated mii port will be disable ( perform /ir_acti function) when low and will be enable when high while the test pin is low. when test pin go high will latch the /dis_dmii signal and this pin perform test mode selection function. nc : when mode= ? 0 ? , this pin keep no connection or pull-up.
AX88860 preliminary asix electronics corporation 11 2.3 expansion bus interface signal name type pin no. description ird[3:0] or /lact[3:0] i/o/z /mh /pu 21-18 inter repeater data : when mode= ? 1 ? , nibble data input/output. transfer data from the ?active? AX88860 to all other ?inactive? AX88860s. the bus-master of the ird bus is determined by ir_vect bus arbitration. /lact[3:0] : when mode= ? 0 ? , those pins drive activity[3:0] leds directly. /ird_v or /lact[4] i/o/z /mh /pu 23 inter repeater data valid : when mode= ? 1 ? ,this signal reflect the rx_dv status of the active port across the inter repeater bus. used to frame good packets. /lact[4] : when mode= ? 0 ? , this pin drives port 4 activity led directly. /ird_er or /lact[5] i/o/z /mh /pu 24 inter repeater data error: when mode= ? 1 ? ,this signal reflect the rx_er status of the active port across the inter repeater bus. used to track receive errors from the phy in real time. /lact[5] : when mode= ? 0 ? , this pin drives port 5 activity led directly. ird_ck or /lact[6] i/o/z /mh /pu 25 inter repeater clock valid : when mode= ? 1 ? ,all inter repeater signals are synchronized to the rising edge of this clock. /lact[6] : when mode= ? 0 ? , this pin drives port 6 activity led directly. ird_odir or /lact[7] o/ml 26 inter repeater data in/out direction : when mode= ? 1 ? ,this pin indicates the direction of data for external transceiver. ?high? = ird[3:0], /ird_er, /ird_v , ird_ck are output. ?low? = ird[3:0], /ird_er, /ird_v , ird_ck are input. /lact[7] : when mode= ? 0 ? , this pin drives port 7 activity led directly. /ir_acto[7:0] or /lpart[7:0] i/o/oc /h 13-9 7-5 inter repeater activity in/out: when mode= ? 1 ? ,when the local repeater activity appearance, the signal of the related rid (repeater id) will be asserted and as a output pin. all other pins serve as input pins but except the collision conditions. when collision occurred all of the signal of related (rid-1) pins will served as outputs and will active during local collision period. the exception case is when rid = 0, then (rid-1) is replaced with (rid+1)=1. /lpart[7:0] : when mode= ? 0 ? , those pins drive partition[7:0] leds directly.
AX88860 preliminary asix electronics corporation 12 2.4 led display signal name type pin no. description led[2:0] or /luti[2:0] o/ml 97-95 led display information : when mode= ? 1 ? , those signals indicate each port?s partition, jabber, activity, collision (global), repeater id, utilization % (global), collision % (global) in sequence. for detail , see the led timing specification /luti[2:0] : when mode= ? 0 ? , those pins drive utilization[2:0] leds directly. the utilization % display define as following : the collision % display define as following : led_ck or /luti[3] o/ml 99 led clock signal : when mode= ? 1 ? , the signal is a discontinue clock for led signals serial shift out. the clock period width is 40ns and last 16 cycle with every 125ms repeated. /luti[3] : when mode= ? 0 ? , this pin drive utilization[3] led directly. note : the utilization % display define as following for mode 0 led direct driving. collision % led0 led1 led2 led3 led4 led5 led6 led7 0 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 2 0 0 1 1 1 1 1 1 5 0 0 0 1 1 1 1 1 10 0 0 0 0 1 1 1 1 15 0 0 0 0 0 1 1 1 20 0 0 0 0 0 0 1 1 30 0 0 0 0 0 0 0 1 60+ 0 0 0 0 0 0 0 0 utilization % led0 led1 led2 led3 led4 led5 led6 led7 0 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 5 0 0 1 1 1 1 1 1 10 0 0 0 1 1 1 1 1 15 0 0 0 0 1 1 1 1 30 0 0 0 0 0 1 1 1 40 0 0 0 0 0 0 1 1 60 0 0 0 0 0 0 0 1 80+ 0 0 0 0 0 0 0 0 utilization % /luti0 /luti1 /luti2 /luti3 /luti4 /luti5 0 1 1 1 1 1 1 1 0 1 1 1 1 1 5 0 0 1 1 1 1 10 0 0 0 1 1 1 15 0 0 0 0 1 1 30 0 0 0 0 0 1 60 0 0 0 0 0 0
AX88860 preliminary asix electronics corporation 13 2.5 miscellaneous signal name type pin no. description lclk i 32 local clock : must be run at 25mhz . used for transmit data to phy devices, /rst i 29 reset : the chip is reset when this signal is asserted low. rst_dly or /lact[d] o/ml 27 reset delay : when mode= ? 1 ? , the signal is active high when reset and delay /rst signal about 2 lclk cycle. it is useful for power on configuration setup control of /ir_acti[7:0]. /lact[d] : when mode= ? 0 ? , this pin drives dedicated mii port activity led directly. daisy_in or nc i/pu 16 repeater identification number daisy-chain in : when mode= ? 1 ? , this pin is a daisy chain serial input for repeater id. a state machine always monitor the input if a correct data (rid) present at the pin, the (rid+1) will be written to rid register and override the power on setup rid for the chip. nc : when mode= ? 0 ? , this pin keep no connection or pull-up. daisy_out or /lpart[d] o/ml 17 repeater identification number daisy-chain out : when mode= ? 1 ? , this pin is periodically shift out the rid of itself to the next chained chip to inform that this id has already been occupied. the rid is shift out periodically every about 200us. /lpart[d] : when mode= ? 0 ? , this pin drives dedicated mii port partition led directly. test i/pd 30 test pin : the pin is just for test mode setting purpose only. must be pull low when normal operation. when in test mode , gep pins will be force to test input signals. rid[2:0] or /lcol, /luti[5:4] i/o /ml /pu 2-1 100 repeater id: when mode= ? 1 ? , repeater id real time input when test pin is low. when test pin go high will latch the rid signals and those pins perform test mode selection function. /lcol , /luti[5:4] : when mode= ? 0 ? , those pins drive collision and utilization[5:4] leds directly. b100 i/pu 94 b100: when logic high 100base-t is selected (default), otherwise 10base-t is selected. mode i/pu 31 mode: repeater chip application mode. mode= ? 0 ? is for single chip repeater application. mode= ? 1 ? is for multiple chips cascaded repeater application. /bridge i/pu 91 /bridge : option for external device type to connect to dedicated mii port. default ?high? is for phy type device. otherwise, ?low? for bridge, switch or mac type device. nc 40 nc : those pins must keep no connection. vdd i 3,22,41 53,64 78,92 power : +5v +/-5% vss i 8,14,15 28,33,38 46,59,65 73,86,93 98 power: 0v
AX88860 preliminary asix electronics corporation 14 3.0 functional description led encoder led display half/full cycle generator utilization rate/ collision rate estimation internal register setup daisy chain for rptr_id cascade arbitration & collision detection txe control repeater sm rxe control fifo receive port multiple xer lact[8:0] lpar[8:0] ljab[8:0] lcol luti[8:0] lcol[8:0] led[2:0] led_ck crs[7:0],dcrs jab[8:0] part[8:0] col tx_rdy 2.5m clk daisy_in daisy_out active[8:0] /rst mode b100 /bridge rid[2:0] col /ir_acto[7:0] rxe[7:0],drxe,rxe_ir txe[7:0],dtxe tx_rdy ird_odir txd[3:0],tx_er rxd[3:0],rx_er,rx_dv,rx_clk drxd[3:0],drx_er,drx_dv,drx_clk rxd[3:0],rx_er,rx_dv,rx_clk ird[3:0],/ird_er /ird_v,ird_ck rd_en jam pattern rptr_id[2:0] per port jabber control per port partition sm crs[7:0],dcrs from the previous chained repeater to the next chained repeater fig - 4 functional block diagram
AX88860 preliminary asix electronics corporation 15 3.1 repeater state machine the repeater state machine is used to control repeater behavior, generates right signal in corresponding states. the repeater state machine is in idle state when there is no carrier presented on any ports . when there is only one port has receive activity, the repeater state machine will enter data - forwarding state to ensure correct data forwarding to other connected ports. if collision happens anytime, the repeater state machine detects collision then send jam pattern to all ports until collision ceases. idle state the idle state happens when these conditions exists: a. /rst is low. b. all crs[7:0] and dcrs are not asserted high in single chip application. c. repeater sense no inter repeater active signal in cascade application, that is, all /ir_acto[7:0] remains high. data forwarding state the state happens when these conditions exists: a. only one signal asserted among crs[7:0] and dcrs in single chip application. b. only one of ir_acto[7:0] become low if in cascade application. the repeater state machine stores receiving packet and transmits to all other ports except for 1. the port is jabbered. 2. the port is isolated. collision state the collision state happens when these conditions exists: a. there are two or more signals asserted high among crs[7:0] and dcrs in single chip system. b. there are two or more signals asserted low among /ir_acto[7:0] in cascade system. c. only one carrier exists but rxdv still low exceeds 4 clock cycles.the repeater sends collision pattern to all ports. one port left state the state happens only when there is no collision but still one port which experienced collision has receive activity. the repeater remains send collision pattern to all ports except the port. 3.2 rxe /txe control idle state the repeater sends no data to any port. rxe(all) = 0, rxe_ir = 0. txe(all) = 0, txe_ir = 0. data forwarding state if active(x) = 1, x is the local connected port, rxe(x) = 1, rxe(all-x) = 0, rxe_ir = 0. txe(x) = 0, txe(all-x) = 1, txe_ir = 1. if active(x) = 1, x is the inter repeater port, rxe(all) = 0, rxe_ir =1. txe(all) = 1, txe_ir = 0. collision state the repeater sends jam pattern to all ports. rxe(all) = 0, rxe_ir = 0. txe(all) = 1, txe_ir = 0.
AX88860 preliminary asix electronics corporation 16 one port left state the repeater sends jam pattern to all other port except for the still activity port. rxe(all) = 0, rxe_ir = 0. txe(all-x) = 1, txe_ir = 0. suppose x is the one left port. 3.3 jabber state machine to prevent an illegally long reception of data from reaching the repeater unit, each port has its own jabber timer. if a reception exceeds this duration (64k bit times for AX88860), the jabber condition will be detected. in this condition, repeater unit will disable receive and transmit packets for the jabbered port and the other ports remain the normal operation. when the carrier is no longer detected for the jabbered port or reset the repeater, the jabber function will be clear and re-enable reception and transmission. 3.4 partition state machine the partition state machine is used to protect network from being upset when a port suffer continuous collision, each port uses a partition state machine to detect and prevent this condition. when a port suffer from continuous 64 times of collision events, then it goes to partition state. the partitioned port will be not released until a packet without collision be transmitted( more than 512 bit times for AX88860) or reset the repeater. 3.5 expansion logic(cascade interface) the expansion logic is used to stack numerous repeaters to expend the number of connected ports. the expansion logic can be divided into two types: expansion logic without buffer (minimum mode) in this mode, use /ir_acto[7:0] to cascade repeaters in back plane. just connect /ir_acto[7:0] of all repeaters without using buffer. this mode is supposed to cascade repeaters on the same board. in this application, the stackable system can reach to 4 repeaters. expansion logic with buffer (maximum mode) this mode is entered with the setting of /dis_dmii = 0, the dedicated port isn?t existed again in this mode. now the dedicated pins drxd[3:0], dcrs, drx_dv, drx_er, drx_clk play a role as ir_acti[7:0]. use /ir_acto[7:0] and /ir_acti[7:0] to cascade repeaters in back plane. buffers are used both in /ir_acto[7:0] and /ir_acti[7:0]. the mode is supposed to cascade repeaters on different boards via cables. in this application, the stackable system can reach to 8 repeaters. /ir_acto<7:0> are driven according to repeater id and receive activity of local connected ports as follows: repeater id idle state only one port activity more than one port activity 000 11111111 11111110 11111100 001 11111111 11111101 11111100 010 11111111 11111011 11111001 011 11111111 11110111 11110011 100 11111111 11101111 11100111 101 11111111 11011111 11001111 110 11111111 10111111 10011111 111 11111111 01111111 00111111 note: all /ir_acto[7:0] will be in open-drain status when they aren?t driven. these signals present high via external pull high resister.
AX88860 preliminary asix electronics corporation 17 3.6 data flow control the signals on the ir bus (such as ird[3:0], ird_v_n, ird_er_n, ird_ck) flow either into or out of the repeater depending upon the repeater?s state. only if the repeater receive packet from local port without collision occurs, the ir signals flow out of repeater. otherwise, these ir signals flow into repeater. in cascade system, it must guarantee that only one repeater drives these signals to avoid contention. 3.7 rid receive-transmit interface(daisy chain logic) in the cascade system, repeater id of each chip will be re-arranged by serial in/serial out daisy chain logic. the logic use daisy_in pin to monitor the rid value of the previous chained chip, and override the original id of the current chip with the value of (rid+1) . use the daisy_out pin to periodically (about 200us) send out the exact rid of the current chip to inform the next chained chip. by this way, each repeater chip in 8 AX88860 stackable application will keep unique id of itself. the rid is used in inter repeater bus arbitration. daisy_in/out frame format idle start bit data0 data1 data2 data3 1 0 rid[0] rid[1] rid[2] parity notes: parity = 1 when sum of 1?s in rid[2:0] is even if no daisy-chain input, that is, daisy_in keep high, the rid of current chip can be clear to 0 during time out period. the timer for time out is about 4sec. there are a input setting , /dis_daisy, which enable/disable daisy-chain function. with the low setting , the rid of current chip don?t care the present data on daisy_in and can?t be overrided. 3.8 led display interface AX88860 provides per-port led status indication for partition, jabber, link/activity and support rate - based led for global utilization (%) and global collision (%).detail function is described on the previous pin description(led interface). led[7:0] are all active low. there are two display ways : complicated and simple way. it depends on the setting of mode. multiple chips cascaded application (mode = 1) led[2:0] status driver wave-form as follows : jab7 jab6 jab5 jab4 jab3 jab2 jab1 jab0 part 7 part 6 led_ck led[0] '0' rid2 rid1 rid0 jab8 part 8 act8 gcol led[1] led[2] d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d11 d12 d13 d14 d10 d15 part 0 part 1 part 2 part 3 part 4 part 5 act0act1act2act3act4act5act6act7 colu 7 colu 0 colu 1 colu 2 colu 3 colu 4 colu 5 colu 6 uti7 uti0uti2uti3uti4uti5uti6 uti1
AX88860 preliminary asix electronics corporation 18 notes: a. part8~0indicates partition status for each port b. jab8~0 indicates jabber status for each port c. act8~0 indicates activity status for each port d. rid2~0 is the id of repeater chip e. colu7~0 indicate global collision rate for each f. uti7~0 indicate global utilization rate for each 104.8ms sampling period. 104.8ms sampling period. it must use external shift register to decode data on led[2:0]. the application shows as follows: 74ls164(#1) 74ls164(#2) q q q q q q q q d d q q q q q q q q part0 part1 part2 part3 part4 part5 part6 part7 jab0 jab1 jab2 jab3 jab4 jab5 jab6 jab7 led[0] led_ck fig - 5 application for led display if the user don?t want to show jabber status, take away the latter 74ls164(#2). the application is the same for led[2:1]. single chip application (mode=0) in this mode, the inter repeater pins are not useful, these pin can be used for display led status directly. then the led application become simple. dump signal dump signal dump signal /ir_acto[0] part[0] ird[0] act[0] led[0] uti[0] /ir_acto[1] part[1] ird[1] act[1] led[1] uti[1] /ir_acto[2] part[2] ird[2] act[2] led[2] uti[2] /ir_acto[3] part[3] ird[3] act[3] led_ck uti[3] /ir_acto[4] part[4] /ird_v act[4] rid[0] uti[4] /ir_acto[5] part[5] /ird_er act[5] rid[1] uti[6] /ir_acto[6] part[6] ird_ck act[6] rid[2] gcol /ir_acto[7] part[7] ird_odir act[7] daisy_out part[8] rst_dly act[8]
AX88860 preliminary asix electronics corporation 19 4.0 internal registers 4.1 configuration register (config) bit bit name default bit description d4 mode 1 mode=1, multiple chip cascade application. mode=0, single chip application. d3 /dis_dmii 1 /dis_dmii= 1, one dedicated port are supported. /ir_acti[7:0] pins are not supported. /dis_dmii = 0, disable the dedicated port and /ir_acti[7:0] pins are supported. d2 b100 1 b100 = 1, all ports are 100mb/ps b100 = 0, all ports are 10mb/ps d1 /dis_daisy 1 /dis_daisy = 1, enable rid daisy-chain function. /dis_daisy = 0, disable rid daisy-chain input: no matter what kind of data input from daisy_in pin the rptr_id can?t be override. d0 /bridge 1 /bridge = 1, the dedicated port connect to phy type device. /bridge = 0, the dedicated port connect to mac or bridge port 4.2 repeater id register(rptr_id) bit bit name default bit description d2-d0 rptr_id[2:0] 111 repeater id : at the rising edge of /rst , the value of rid[2:0] are latched in this register as rptr_id[2:0]. the value can be override according to the data from serial daisy-chain daisy_in pin except /dis_daisy is configured to ?low? .
AX88860 preliminary asix electronics corporation 20 5.0 electrical specification and timing 5.1 absolute maximum ratings description sym min max units operating temperature ta 0 +70 c storage temperature ts -55 +150 c supply voltage vcc -0.5 +7 v input voltage vin vss-0.5 vdd+0.5 v output voltage vout vss-0.5 vdd+0.5 v lead temperature (soldering 10 seconds maximum) tl -55 +250 c note : stress above those listed under absolute maximum ratings may cause permanent damage to the device. exposure to absolute maximum ratings conditions for extended period, adversely affect device life and reliability 5.2 general operation conditions description sym min max units operating temperature ta 0 +70 c supply voltage vdd +4.75 +5.25 v 5.3 dc characteristics (vdd=4.75v to 5.25v, vss=0v, ta=0 c to 70 c) description sym min max units low input voltage vil vss-0.5 0.8 v high input voltage vih 2 vdd+0.5 v low output voltage vol 0.4 v high output voltage voh 2.4 v input leakage current 1 (note 1) iil1 10 ua input leakage current 2 (note 2) iil1 500 ua output leakage current iol 10 ua note : 1. all the input pins without pull low or pull high. 2. those pins had been pull low or pull high.
AX88860 preliminary asix electronics corporation 21 5.4 ac specifications 5.4.1 mii interface timing tx & rx t0 t1 lclk t2 t2 tx_en t3 t3 tx_er txd symbol description min typ. max units t0 local clock cycle time 39.996 40 40.004 ns t1 local clock high time 14 20 26 ns t2 tx_en delay from lclk high 7.440 21.760 ns t3 tx_er or txd delay from lclk high 3.410 13.320 ns t4 t5 rx_clk crs t6 t7 rxe t8 rxdv t9 rxd rxer
AX88860 preliminary asix electronics corporation 22 symbol description min typ. max units t4 rx_clk clock cycle time 39.996 40 40.004 ns t5 rx_clk clock high time 14 20 26 ns t6 crs to rxe assertion delay 20 ns t7 crs to rxe de-assertion delay 160 200 ns t8 crs to rxdv delay requirement 40 160 ns t9 rxd or rxdv or rx_er setup to rx_clk rise time 10 - ns 5.4.2 expansion bus crs t1 t2 ird-odir ird_ck t3 ird[3:0] t4 /ird_er t5 t6 /ird_v symbol description min max units t1 crs assertion to ird-odir assertion - 20 ns t2 crs de-assertion to ird-odir de-assertion 160 200 ns t3 ird[3:0] setup time to ird-ck high 10 - ns t4 /ird_er setup time to ird-ck high 10 - ns t5 /ird_v setup time to ird-ck high 5 - ns t6 /ird_v hold time from ird-ck high 5 - ns
AX88860 preliminary asix electronics corporation 23 5.4.3 led display t3 led_ck -------- - ~ ~ ------- d0 d1 d2 .............. d14 d15 d0 d1 d2 t4 t3 led_ck t1 t2 led[2:0] d0 d1 d2 d3 ------- d15 d0 symbol description min typ. max units t1 led setup to led_ck high 190 200 ns t2 led hold from led_ck high 200 210 ns t3 led_ck period width 400 ns t4 continuous 16 led_ck cycle time 52.4 ms 5.4.4 led display after reset /reset t1 t2 t2 t2 t3 led[2:0] symbol description min typ. max units t1 repeater reset time 1000 ns t2 led blink time after reset 838.4 ms t3 led dark time before normal display 419.2 ms
AX88860 preliminary asix electronics corporation 24 5.4.5 repeater id daisy chain t1 t2 t2 daisy-out id0 id1 id2 id0 id1 id2 t3 daisy-in id0 id1 id2 id0 id1 id2 symbol description min typ. max units t1 daisy chain one burst period 204.8 us t2 start bit period or data width 12.8 us t3 time-out occur when no data present on daisy_in * 3.8 s note : daisy-chain data-in time-out stands for no input data (always high level) for the specific time.
AX88860 preliminary asix electronics corporation 25 6.0 package information b e d hd e he pin 1 a2 a1 l l1 q milimeter symbol min. nom max a1 0.05 - 0.25 a2 2.55 2.65 2.75 b 0.25 0.30 0.40 d 13.80 14.00 14.20 e 19.80 20.00 20.20 e 0.65 hd 17.60 17.90 18.2 he 23.60 23.90 24.2 l 0.60 0.80 1.00 l1 2.00 q 0 8

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